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NXP Semiconductors /MIMXRT1052 /IOMUXC_SNVS /SW_MUX_CTL_PAD_PMIC_STBY_REQ

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Interpret as SW_MUX_CTL_PAD_PMIC_STBY_REQ

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

MUX_MODE=ALT0, SION=DISABLED

Description

SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: ccm

5 (ALT5): Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5
SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad PMIC_STBY_REQ

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data